Verilog编写的简单异步串口 完全原创，站长请查看内容

This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.

ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging

利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤(rs code in FPGA)

FPGA入门点亮一个LED灯，作为FPGA入门级程序(FPGA is)

基于DB8小波变换的verilog代码设计，支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)

adc0809的fpga时序电路接口程序-Sequential Circuits adc0809 the FPGA interface program

绝热电路都是使用"可逆逻辑"的低功耗电路以节省能源。与传统的CMOS电路，在开关过程中消耗能量，不同绝热电路试图节约费用由以下两个关键的规则： 永远不会打开一个晶体管时电压源之间

用于压缩感知 OMP 算法非常适合于压缩感知