简单电子玩具的感知模块程序设计,通过外部输入信号改变内部信号.从而改变玩具的状态

DEBOUNCEfpga的实现，运用软件实现数码管的变化(fpga of the)

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2

一个7段的显示器，及按一定顺序循环得到的结果，可重复使用(A 7-segment display, and by a certain sequence and cycle the results obtained can be reused)

实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)

闪耀光栅 有带阻滤波器作用的闪耀光纤光栅，反射角度可以控制(Blazed grating)

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

ＦＰＧＡ与ＳＤＲＡＭ　的　ＶＨＤＬ　接口设计(ｔｈｅ　interface of FPGA and SDRAM)