基于FPGA的红外图像预处理系统的研究与设计，给fpga工程技术人员一个参考...

EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)

uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file

一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler

通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role

一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)

at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)

Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written

Description of a sistolic arhictecture for a FFT implementation in FPGA.

writing testbench in system verilog