基于FPGA的红外图像预处理系统的研究与设计，给fpga工程技术人员一个参考...

一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated

Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)

完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)

使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形(use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms)

一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)

用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game