HDLC接口协议的FPGA实现使用verilog

两个例子提醒我们如果我们要使用锁存器则不需要任何操作，如果我们想避免锁存器的话，我们要让这个元器件的每一个可能条件赋予一个值-signal or variable "" may not be assigned a new value in every possible path through the Process Statement

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)

fpga学习中常用的缩略语-commonly used abbreviations

Altium Reference design for LMH0340 test bed and design

verilog_ad0809 cpld control

关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures

The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.

电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA

Mini AES Advanced Encryption Standard (AES) implementation with small area/resources utilization. Features - Encryption and Decryption unit in single core.