HDLC接口协议的FPGA实现使用verilog

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

说明：  (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig

超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)

设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.

ofdm_cp_insertion add/remove CP

51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)