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VERILOG-CAR-TEST
基于FPGA的Verilog语言的智能小车,已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)
- 2020-11-26 19:39:32下载
- 积分:1
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seven_persons
自己写的7人表决器的verilog程序,实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)
- 2013-08-10 07:15:06下载
- 积分:1
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hammingaTB
Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.
- 2013-11-06 15:45:02下载
- 积分:1
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LMP
利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP
- 2022-01-25 18:35:46下载
- 积分:1
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High Speed dd
说明: (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
- 2020-06-24 08:40:01下载
- 积分:1
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CLA
超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)
- 2007-11-14 20:26:59下载
- 积分:1
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设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。...
设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
- 2022-02-04 07:33:00下载
- 积分:1
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ofdm_cp_insertion
ofdm_cp_insertion add/remove CP
- 2015-01-29 21:25:47下载
- 积分:1
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UC1676C
51单片机测试程序,IC:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)
- 2020-10-17 11:17:28下载
- 积分:1
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06219426Spartan3E
VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)
- 2011-02-10 09:41:12下载
- 积分:1