HDLC接口协议的FPGA实现使用verilog

说明：  BUS documentation and map reffereces

使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.

basic verilog code on siso, piso, sipo

modelsim crack versin 6

verilog vga 图像处理(verilog vga)

这段代码是用来实现二维高斯滤波器的。

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

这个

VHDL常用实例，适合初学者，有计时器等常用例子-Common examples of VHDL, suitable for beginners, there are examples of commonly used timer, etc.