UART的源（格版）

matlab仿真2ask和4ask.可观察信号的时域波形和频谱图。(Matlab simulation 2ask and 4ask. Can observe the signal time domain waveform and spectrum.)

说明：  fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)

8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......

数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)

verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)

数字钟(Digital clock)

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

lab report for lab 4

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

最终FFT 64点使用定点。