Some useful things to know about picoblaze microcontroller.

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

Ethernet MAC-MII interface of Transmit

these files are written in verilog but i am uploading in text format

加减可控制的十到十六进制计数器。完全准确，可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)

Verilog OTP ROM source code

说明：  perl学习资料，包含一些常用的一些文档，可直接做来用于实践(perl training)

该项目实现了在Altera FPGA中的乒乓球比赛。游戏控制器是建立在FPGA中。玩家使用它连接到FPGA开发板玩的游戏键盘。本场比赛显示VGA屏幕上。所有部件，如键盘，VGA屏幕是由控制装置控制。

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)

8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn