fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

液晶的控制，有VHDL语言实现-lcd control

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

VHDL code for 32 byte RAM

以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)

说明：  详细介绍了如何使用ModelSim进行仿真.(it will teach you how to use the ModelSim to simulink.)

硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation