fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...

this come from alter ,you can look and find it on line about h263.

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

AMBA总线的AHB+APB源程序，供初学者学习。(Verilog for AHB and APB)

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support

交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．-Verilog realize traffic lights, with detailed notes in Chinese.

qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)