基于altera系列芯片lvds接口的fpga设计 verilog源码

这个文件中是UltraEdit的一些格式化文件说明 由于原来的 UltraEdit 不支持 HDL 语言的格式化显示，把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt

A counter that starts from 0 and increments mod 16 on each rising edge of the clock

说明：  verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是21-50个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here are 21-50 months

加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息. // 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测. // 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电 // 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)

《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2