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UART
基于FPGA设计的串口发送及接收程序,波特率可调(FPGA - based serial port sending and receiving)
- 2020-06-18 23:20:01下载
- 积分:1
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PWM
verilogHDL语言编写,简单的FPGA脉冲程序,初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)
- 2012-12-27 11:54:45下载
- 积分:1
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基于FPGA 的usb传输
利用FPGA实现USB芯片CY7C68013与上位机的进行通信的系统,代码采用VHDL语言实现,利用状态机实现FPGA控制USB的数据传输,传输时序采用SLAVE FIFO实现
- 2022-03-05 23:47:35下载
- 积分:1
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master_slave
AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分:1
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clk_div3
在fpga中对于pll无法完成的分频,可采用计数方式,本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分:1
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verilog支持noise噪声的端口port
verilog支持noise噪声的端口port, 可以用于仿真运行.
评估噪声影响
Verilog port that supports noise and can be used for simulation run.
Evaluate noise effects
- 2022-07-25 10:35:21下载
- 积分:1
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ldpc_decoder_802_3an
LDPC的编码模块和解码模块,实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)
- 2018-07-23 15:01:20下载
- 积分:1
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EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。...
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
- 2022-10-28 17:25:03下载
- 积分:1
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rectifier
三相PWM整流,实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ,can maintain the stable DC voltage)
- 2012-11-28 09:19:54下载
- 积分:1
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jt2
基于FPGA的交通灯代码,VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)
- 2013-10-26 13:30:26下载
- 积分:1