verilog HDL verilog HDL verilog HDL

初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)

可供初学者学习 比较简单 一读就能明白 LED7数码显示程序(Relatively simple for beginners to learn the first reading of the digital display program will be able to understand LED7)

This is counter with T_FF.

说明：  八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)

Use verilog language design DIGITAL-PID source

占空比1：1的通用分频模块-1:1 generic-frequency module

说明：  report for a report for a class

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)