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verilog for full_adder
verilog for full_adder
- 2022-06-28 14:23:05下载
- 积分：1
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一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source
- 2022-02-19 22:00:27下载
- 积分：1
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１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用...
１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
- 2022-03-04 05:06:34下载
- 积分：1
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weifenqi
微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)
- 2020-12-01 10:39:28下载
- 积分：1
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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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vhdl4
VHDL Language Reference courses part4
- 2010-02-10 00:52:53下载
- 积分：1
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verilog
关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分：1
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SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
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verilog hdl verilog hdl verilog hdl
verilog hdl verilog hdl verilog hdl-verilog hdl
- 2022-07-23 23:39:39下载
- 积分：1
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用VHDL语言在CPLD上实现串行通信
用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
- 2022-02-15 15:58:59下载
- 积分：1
