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vhdl 基于ADC0809 A/D转换控制器的设计实验
vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809
- 2022-02-25 21:38:23下载
- 积分:1
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Taxi-automatic-billing
出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)
- 2009-10-08 10:07:15下载
- 积分:1
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counter
说明: 基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)
- 2020-06-20 21:00:01下载
- 积分:1
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Flash接口控制器的VHDL和Verilog源代码和程序测试
flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
- 2022-06-27 08:57:14下载
- 积分:1
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xilinx simulator programme of serial port
xilinx的串口仿真程序-xilinx simulator programme of serial port
- 2022-11-08 03:05:05下载
- 积分:1
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A-Memristor-SPICE-Model
一篇讲述如何在pspice软件中仿真忆阻器(memristor)替代蔡氏混沌电路中的非线性电阻进而观察研究混沌相图的文献(How about a software simulator pspice memristor (memristor) alternative Chua' s chaotic circuit chaotic nonlinear resistance and then observe the phase diagram of the literature)
- 2011-11-17 16:04:55下载
- 积分:1
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ASYNC_FIFO_SYNTH
This file contains async fifo design
- 2014-03-01 20:48:22下载
- 积分:1
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ahb2apb_bridge_verification-master
ahb to apb master verification
- 2021-03-23 22:09:15下载
- 积分:1
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RISC-V-Reader-Chinese-v2p1
RISC-V 芯片设计规范,很有参考价值,开源芯片设计必备参考资料,希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分:1
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gtx_drp
高速串行设计FPGA-GTX IP设置生成drp模块,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
- 2021-01-19 22:38:43下载
- 积分:1