VHDL学习总结，简要概括了VHDL，非常适合做学习的总结

本系统用于GPS中频部分的窄带滤波（AD后的数据经过LMS滤波后去掉窄带干扰，可以抑制20dB以上的干扰）(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)

VHDL Programmes -2 for dumping on FPGA

RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure

通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

this program is a simulation for Aloha

在vhdl开发环境下，关于协议PS2 verilog 源码-In VHDL development environment, with regard to the agreement PS2 verilog source code

VHDL语言的cookbook,能够使你更快的学会使用VHdL-cookbook

加扰器解扰器设计,组合逻辑电路可以选用下述不同的逻辑类型来实现：互补CMOS结构、有比电路、差 分共源-共栅电压开关逻辑（DCVSL），传输门逻辑、互补传输晶体管逻辑（CPL）或动态电 路结构，也可以是以上不同类型结构的混合。(Scrambler/ descrambler design)

很好的tft参考实列，通用的8位并口，非常快移值-Tft good reference is listed, eight general-purpose parallel port, very fast shift value

A counter that starts from 0 and increments mod 16 on each rising edge of the clock