VHDL学习总结，简要概括了VHDL，非常适合做学习的总结

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog description of

计时范围为59.99秒；有计时开始和停止计时控制，复位控制可以对所有计时进行异步复位；计时结果由四位七段数码管显示。

用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

ALTERA on chip fifo. this document is from altera. good resouce

脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source

说明：  用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator