通过实例的VHDL程序设计

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)

-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-

K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料-K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D Samsung 4G 8G 16G nand datasheet

实现简单自动售货机的基本功能。投币找零功能，并用Led数码管显示，输出结果用Led显示。(Basic functions simple vending machines. Coin change for function and use Led digital tube display, the output display Led.)

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl　adder vhdl　adder vhdl　adder

Verilog编程语言经典手册Classic Manual Verilog programming language(Verilog programming language classic manual Classic Manual Verilog programming language)

说明：  iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现(iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation)

字长可以简单调整，即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)