通过实例的VHDL程序设计

说明：  基于FPGA的信号发生器，产生了正弦波，方波，锯齿波和三角波四种波形，按下一次按钮，波形切换一次。按下另一个按钮，改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)

介绍了硬件语言的仿真软件modelsimse的操作是使用方法，可以为入门的参考资料-Introduction of the hardware language modelsimse operation simulation software is to use the method of reference for the entry

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

应用背景此代码是用于执行器和传感器，可以在网络中实现一个很好的连接与其他节点和主。关键技术VHDL代码 ；可以控制位CRC校验和填料-掩模的验收规范

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

用于实现fpag-cpu的数据通路源代码。用vhdl编写，包括内存，寄存器组，和alu（简陋的alu，仅包含加法器）三大部分通过手动微指令输入信号，可以往内存写入数据，并加载到寄存器组中，通过alu产生结果，结果保存在一个锁存器中，可以把结果写回寄存器组或者内存。本人在quartus下编写仿真通过。附件中未给出相关工程文件。

本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.

DE2-70开发板中附带的控制面板，可以读取存储器中的数据，这个可以正常连接和读取，有好几版本的，有的不能用，而这个经过我亲自测试。(DE2-70 development board comes with a control panel, you can read the data in the memory, this can be properly connected and read, there are several versions, and some can not be used, and this after I personally tested.)

dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)