通过实例的VHDL程序设计

dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates

fft快速傅立叶变换源码-the source of fast fft transform

spartanII 是xilinx公司提供的一款高性能FGPA芯片,本文详细介绍spartanII的体系结构和编程!-spartanII Xilinx is provided by a high-performance chip FGPA, spartanII This paper describes the architecture and programming!

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.

24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。(24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.)

Modelsim 5.6 se 简易使用教程 -Modelsim 5.6 se easy to use tutorial

电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)