通过实例的VHDL程序设计

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)

Matlab to hdl code for Least_square testbench

使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域

QuartusII多路选择器,数字电路环境，大三EDA技术实验(Quartus,chosen conductos in matheathics field)

主要介绍了ＦＰＧＡ设计的基本原则、基本设计思想、基本操作技巧、常用模块。-Mainly introduces the basic principles of FPGA design, basic design concepts, basic operating skills, commonly used modules.

4-Bit BCD Adder in Verilog

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)

对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder