多个VHDL编码的例题，详细的电路图介绍，还有流程图

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR

altera EP1C6Q240C6开发板原理图-altera EP1C6Q240C6 SCH

Cypress USB 的主从FPGA 控制实现代码(USB controller)

0-99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦 -0-99 notation VHDL source, comprehensive guide book on the experiment can be used by everyone to download Oh

等精度测频原理的频率计程序与仿真。。希望大家能用的到撒(such precision frequency measurement principles of Cymometer procedures and simulation. . Hope everyone can withdraw to the)

these files are written in verilog but i am uploading in text format

用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.

项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。

完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry