VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助...

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)

Universal Shift Register

FIR有限冲击响应下带通滤波器的构建及滤波器仿真（通过matlab和simulink两种方法实现）(FIR finite impulse response bandpass filter and filter simulation (via two methods matlab and simulink))

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

说明：  这是一个关于dQPSK的Matlab程序 这是一个关于dQPSK的Matlab程序 (This is a dQPSK the Matlab program This is a dQPSK the Matlab program)

支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)

用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)

Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.

Fast Fourier Transform (FFT) 32K Point Design contains information about the design example