VHDL、Verilog HDL语言，是华为公司的技术指导书，希望对你有所帮助...

自己写的pwm占空比采集与输出 但是没有计算占空比，如果又需要可以自己修改计算并显示占空比，该程序已经测试过了，可以使用，拿出来供大家分享，新手写的如有不足请大牛带飞。

用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test

processor design istruction load pipeline ,hazard

这是介绍嵌入式开发相关的资料。有总线与内存的操作-introduced Embedded Development relevant information. Bus and a memory operation

vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners

用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.

SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)

一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

基于VHDL的抢答器程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-Answer Based on the VHDL program, including complete source code, locking pin, as well as download files documents can be directly downloaded using