VHDL编程语言设计，显示灯，显示VHDL字样。

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users

VHDL的应用：USB-BLASTER的原理图-VHDL FOR USB-BLASTER

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

It is Synopsys dmac controller databook

VHDL数字电路设计的电子书，很好的学习材料-VHDL digital circuit design of e-books, very good learning materials

simple code based on verilog shifter , cla ,clg

SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore

正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)

verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!