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使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟...
使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
- 2022-06-20 16:23:08下载
- 积分:1
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ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户
ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
- 2022-02-25 00:06:16下载
- 积分:1
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VHDL的应用:USB
VHDL的应用:USB-BLASTER的原理图-VHDL FOR USB-BLASTER
- 2022-04-23 08:50:27下载
- 积分:1
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SimpleVOut-master
说明: SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分:1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分:1
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E VHDL数字电路设计
VHDL数字电路设计的电子书,很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
- 2023-01-18 23:30:04下载
- 积分:1
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基于Verilog代码简单
simple code based on verilog
shifter , cla ,clg
- 2023-09-01 00:50:02下载
- 积分:1
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SPI串口的内核实现spicore
SPI串口的内核实现spicore
SPI串口的内核实现spicore
SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string
mouth essence to realize spicore the SPI string mouth essence to
realize spicore
- 2023-06-28 18:20:03下载
- 积分:1
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data_rom
正弦信号发生器,用VHDL来完成,抗干扰能力较强,(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)
- 2009-07-15 22:44:02下载
- 积分:1
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verilog实现ALU的源代码,并提供了详细的测试平台!
verilog实现ALU的源代码,并提供了一个详细的测试平台!-achieve ALU Verilog source code, and provide a detailed test platform!
- 2022-03-15 13:01:46下载
- 积分:1