sin and cos with cordic VHDL

its a Fifo BASED design i also Interface DAC2904

cm12864液晶显示器的vhdl驱动代码，基于状态机的转换，实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.

实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

工作机制如下： 1、 系统上电,配置信息由片外加载到片上配置存储器中; 2、 执行某算法前，将此算法所有的配置包写入到配置包存储器中（配置包存储器包含在配置解析单元中）; 3、 配置解析单元解析配置索引,从配置存储器中选择相应的配置对可重构阵列及功能模块进行配置； 4、 阵列从外部中读取数据进行计算，计算结果写出到密文寄存器中； 5、 可重构阵列与功能模块计算的中间结果数据只与通用寄存器堆进行交互； 6、 阵列计算的中间结果通过通用寄存器堆缓存；

可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.

mult,在quartusII中，以模块输入形式，仿真乘法器mult，得到时序图和功能图(a simulation example of mult)

这份代码完成的功能是通过蜂鸣器播放《梁祝》这首曲子，当然可以自行更改代码，以播放其它的乐曲，所用的硬件描述语言是VHDL，代码有四部分构成，顶层模块、预分频模块（产生基频）、音乐表格和分频模块（产生所需的各音调）。

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit