可综合的vhdl设计特点.pdf

VGA 640x480 driver in verilog

HDL example source code 1/5 tff_a

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

EMP3064的开发板板，原理图，verilog例子，板子说明，规格书，全套资料(EMP3064 development board, schematics, Verilog examples, board instructions, specifications, a full set of information)

说明：  Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes. The representation step specifies the mapping the phenotypes onto a set of genotypes. Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space. Chromosome, and individual can be used for points in the genotye space. Elements of a chromosome are called genes. A value of a gene is called an allele. Variation Operators The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.

16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)

基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en(UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data)

说明：  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

there are exemple in the vhdl

VHDL cyclic redundancy check generator und receiver