登录
首页 » VHDL » Music_Player

Music_Player

于 2022-11-10 发布 文件大小:2.73 kB
0 179
下载积分: 2 下载次数: 1

代码说明:

这份代码完成的功能是通过蜂鸣器播放《梁祝》这首曲子,当然可以自行更改代码,以播放其它的乐曲,所用的硬件描述语言是VHDL,代码有四部分构成,顶层模块、预分频模块(产生基频)、音乐表格和分频模块(产生所需的各音调)。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • UART
    A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
    2009-12-24 00:04:13下载
    积分:1
  • i2c
    说明:  I2C完整代码,可综合,可仿真,已经过验证(I2C code can been syn and simulation ,veritify)
    2021-02-26 13:11:46下载
    积分:1
  • Hardware-CNN-master
    Convolutional neural network code for fpga
    2019-02-27 15:21:22下载
    积分:1
  • 占空比1:1的通用分频模块
    占空比1:1的通用分频模块-1:1 generic-frequency module
    2022-11-11 08:45:03下载
    积分:1
  • LS165
    LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
    2020-11-22 22:59:34下载
    积分:1
  • gtwizard_254_127_ex_1113_3
    说明:  配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
    2019-06-17 21:33:56下载
    积分:1
  • source
    altera DDR3 逻辑测试代码,这是工程实际调试好的代码,保证能用。(altera DDR3 vhdl code)
    2020-12-21 20:49:08下载
    积分:1
  • simple code based on verilog shifter , cla ,clg , ALU , PC
    simple code based on verilog shifter , cla ,clg , ALU , PC
    2022-03-04 03:11:05下载
    积分:1
  • gtx_drp
    高速串行设计FPGA-GTX IP设置生成drp模块,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
    2021-01-19 22:38:43下载
    积分:1
  • vhdl实现的鼠标协议,代码可读性高,适合作为参考案例。
    vhdl实现的鼠标协议,代码可读性高,适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.
    2022-02-06 08:18:06下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载