其基于FIFO的设计

基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)

saa7113_配置.SAA7113视频解码系列芯片的一种，8位彩色配置(saa7113_ configuration. SAA7113 video decoder chips in an 8-bit color configuration)

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

fpga DCM使用教程 好几个文档 帮助您一次学会使用DCM(fpga the DCM using the tutorial a few documents to help you first learn to use the DCM)

FPGA课程设计源码，整合VGA,PS2键盘，CORDIC三角函数算法，在basys2平台上使用完全可行。(FPGA curriculum design source, integrated VGA, PS2 keyboard, CORDIC trigonometric algorithm, used on basys2 platform entirely feasible.)

256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

turbo product code used in error correction

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)