开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟...

可生成rom.初学者可以看看。很不错的。理解后生成rom很容易的。(LPM_ROM .It is good for VHDL new learner)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

适应多个模式的rs编码，Verilog，选择对应的多项式(RS coding adapted to multiple modes.)

AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.

EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals. )

Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。(Verilog code, suitable for beginners to learn, is based on the DE2 platform code.)

使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)

VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code

用VHDL语言实现数字钟的设计，要求设计实现一个具有带预置数的数字钟，具有显示年月日时分秒的功能。用6个数码管显示时分秒，set按钮产生第一个脉冲时，显示切换年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒，第 8个脉冲到来后预置结束，正常工作，显示的是时分秒。Up为高电平时，upclk有脉冲到达时，预置位加1.否则减1。

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)