用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL...

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display

verilog coding for butterworth filter with cut off frequency with 500hz

12232型号LCD液晶屏显示程序，简单易懂(12232 Model LCD screen display program, easy to understand)

《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7

32bit floating point addition

任意维数矩阵求逆的fpga实现，矩阵求逆是矩阵运算中最重要且最难实现的一种运算(fpga implementaion of matrix inverse of any dimension)

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example