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高级加密标准AES的FPGA实现,支持128,256密钥长度格式
高级加密标准AES的FPGA实现,支持128,256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
- 2022-03-25 02:47:08下载
- 积分:1
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警卫控制系统,主要 控制 电梯系统 ,通过422通讯格式完成与电梯系统之间的 通讯协议。...
警卫控制系统,主要 控制 电梯系统 ,通过422通讯格式完成与电梯系统之间的 通讯协议。-Security control system, the main control elevator systems, through to complete the 422 communication format, communication protocol between the elevator system.
- 2022-01-25 18:31:08下载
- 积分:1
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design-of-CAN-based-on-VHDL
基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计,实现其功能,并且能够在FPGA开发平台Quartos上通过仿真验证,证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)
- 2011-07-22 15:22:27下载
- 积分:1
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Can be directly used for engineering applications of CRC checksum inside VHDL co...
可以直接用于工程应用的crc校验VHDL编码
里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications
- 2022-08-03 19:10:27下载
- 积分:1
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FPGA RAND 生成伪随机数
FPGA生成伪随机数,希望对加密的童鞋有用(FPGA generates pseudo-random numbers, we want to be useful)
- 2013-08-05 16:43:55下载
- 积分:1
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SSI-ABZ
SSI转ABZ信号FPGA程序,测试完全可用(Function of SSI convert to ABZ signal,is available)
- 2019-05-19 15:37:48下载
- 积分:1
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zidongshouhuoji
使用VHDL语言实现的一个自动售货机的程序。适合VHDL初学者使用。(VHDL language using a vending machine program. VHDL suitable for beginners.)
- 2011-04-29 21:28:00下载
- 积分:1
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实用的程序代码,希望对大家有用,已经调试通过
实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
- 2022-09-21 12:35:03下载
- 积分:1
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FIR滤波器的基本Verilog代码实现
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2023-05-26 13:40:03下载
- 积分:1
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pipline_lms_and_rls_verilog
流水线LMS,和RLS算法的Verilog代码,用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
- 2021-05-06 20:58:37下载
- 积分:1