用verilog实现FSK调制，称为IP核来实现模块…

Free 8051 core upload

Visual Basic 编写的，为程序增加扫描功能-Written in Visual Basic, in order to increase the scanning process

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

quartusII的使用说明书，特别适用于初学者使用。-quartusII the use of brochures, especially for beginners to use.

VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

最完整最实用的8051的软核，用VHDL语言编写全部原代码，并有详细的注释介绍，对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference

这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。

1024点fft verilog hdl-1024-point fft verilog hdl

《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4

说明：  DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)