DDR SDRAM information, interested to see friends down under

基于FPGA的PCM编码器与解码器的设计-about fpga and pcm

关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL

用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine

应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码，华勒斯树和超前进位addder关键技术超大规模集成电路设计，通信和DSP的应用，芯片设计，VHDL，Verilog程序，加法器和乘法器

说明：  试用Verilog HDL语言，设计十进制计数器，将计数过程用一个数码管进行显示（0～9）。要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)

FPGA简单VGA彩条显示程序驱动程序640*480(FPGA simple VGA color display Driver 640* 480)

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

整合的OFDM调制解调方法，matlab文件，modelsim仿真(Integration OFDM modulation and demodulation method, matlab file, modelsim simulation)

一些对初学者比较实用的源码，ASK，PSK，FSK调制解调(Some of the more practical source code for beginners)

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)