VHDL prepared by the FIR filter source for Embedded designers have a good role i...

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

VHDL编程语言设计，显示灯，显示VHDL字样。-VHDL programming language design, indicator lights, indicating the word VHDL.

verilog da0832 cpldfpga control-verilog da0832 cpldfpga control

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing

Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera

Enhanced Audio Project by Dixie Xue & Wei Zhang -Enhanced Audio Project by Dixie Xue & Wei Zhang

利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)

spartan 3E和verilog HDL的初学者极好的教材，本程序可直接下载到spartan实验板上运行。(Spartan 3E and Verilog HDL beginners excellent materials, the program can be downloaded directly to the spartan experimental board run.)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)