VHDL prepared by the FIR filter source for Embedded designers have a good role i...

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)

应用背景在本文中，一个高性能和高度优化Rijndael AES算法的硬件实现了设计并实现Xilinx Virtex-5 xc5vlx50FPGA器件。设计采用模块化利用VHDL语言的方法。设计工作正确如图所示。这个所提出的设计的性能进行评估的基础上吞吐量和面积。我们的设计利用了速度339.087兆赫，这意味着吞吐量4.34用399片Virtex-5 FPGA面积Gbps。关键技术本文提出了一种有效的Rijndael算法的硬件实现高级加密标准（AES）加密算法采用最先进的现场可编程门阵列（FPGA）。在非常高速集成电路设计的设计硬件描述语言（VHDL）。时序仿真进行验证所设计的电路的功能。性能评估也做了吞吐量和区域。在国家的最先进的Xilinx Virtex-5实现设计（xc5vlx50ffg676-3）FPGA实现吞吐量4.34千兆位/秒，总共使用了399片。

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS

LDPC码的短循环对LDPC码性能的影响 (Short Protograph-Based LDPC Codes)

Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )

说明：  BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

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fpga核心源码，有利于学习，适合初学者学习-fpga core source code, there is conducive to learning, suitable for beginners to learn