FPGA数字AGC(帮同学做的毕业设计)

初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information

RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)

基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar )

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)

VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子(Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of)

有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.

CH2CH1VHDL 数字电路参考书所有程序4-CH2CH1VHDL digital circuit reference all proceedings 4

这是一个GPIB源程序代码,里面有硬件相对应的代码-This is a GPIB source code, which corresponds to a hardware code

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)