FPGA数字AGC(帮同学做的毕业设计)

数码管显示程序，可以显示当前的数值，可以动态显示和静态显示 可以选择显示方式-Digital tube display program can display the current value, you can dynamically display and static displays can choose to display

采用VHDL语言实现基于ＢＭ算法的ＲＳ译码器，附件为整个工程文件，内附波形仿真图。程序在QUARTUS II 9.0下仿真通过

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures

DDS VHDL include everything of dds AD9914

说明：  用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )

ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)

credit base network on chip(network on chip (noc))

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)