应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多...

VHDL常用源程序，希望以EDA技术学习者有用！-VHDL source code commonly used, I hope to EDA technology learners useful!

adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

offset_cancellation code for matlab to hdl

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

Verilog reference book

介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处-Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License