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24,60,100进制的计数器,还有数字时钟,欢迎下载哦~
24,60,100进制的计数器,还有数字时钟,欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~
- 2022-11-11 21:25:03下载
- 积分:1
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SRAM6bit
sram 6bit仿真模型,verilog编写(sram 6bit simulation model, verilog prepared)
- 2021-03-16 13:59:22下载
- 积分:1
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Asqare
用fpga实现的连连看游戏,功能还不完善,不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)
- 2012-08-27 18:39:59下载
- 积分:1
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tb_time_offfset
说明: offset_cancellation code for matlab to hdl
- 2020-06-17 12:20:02下载
- 积分:1
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This code implements the output shift register functions, beginners can learn to...
本代码实现了输出移位寄存器功能,初学者可以借鉴学习-This code implements the output shift register functions, beginners can learn to learn
- 2022-06-20 09:32:02下载
- 积分:1
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digital-design-and-synthesis
Verilog HDL 数字设计与综合,夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证,不仅讲解语法,更从基本概念讲起,逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)
- 2012-10-23 00:16:59下载
- 积分:1
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dct01
Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)
- 2011-01-17 02:40:41下载
- 积分:1
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buffer for in/out data.
buffer for in/out data.
- 2023-02-22 20:05:04下载
- 积分:1
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以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。...
以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.
- 2023-08-25 00:30:05下载
- 积分:1
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VHDL language used to write the VGA control procedures have been verified, the a...
用VHDL语言写的VGA 控制程序,已经验证过,绝对好用!-VHDL language used to write the VGA control procedures have been verified, the absolute ease of use!
- 2022-01-23 11:20:28下载
- 积分:1