4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the program to set the number of bits, there is a very good scalability.

高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching

代码实现了一个根升余弦成型滤波器，2PAM信号通过此成型滤波器，并且匹配接收，画出了发送和接收波形，验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)

使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.

理想三相转单相 基于 spwm 的逆变器，可调(Ideal three-phase switch to a single the phase based spwm inverter)

可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。-QuartusII-based environment to create the form of modular composite video sync signal.

本文提出了一种新颖的可逆乘法器。可逆逻辑可以发挥重要作用