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verilog程序设计教程,适合初学者。
verilog程序设计教程,适合初学者。-verilog programming tutorial for beginners.
- 2023-03-06 05:00:04下载
- 积分:1
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供大家学习以太网VHDL和Verilog代码
以太网的vhdl和verilog代码,供大家学习-Ethernet VHDL and Verilog code for everyone to learn
- 2022-08-21 10:09:17下载
- 积分:1
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quartus-mult
mult,在quartusII中,以模块输入形式,仿真乘法器mult,得到时序图和功能图(a simulation example of mult)
- 2012-10-17 14:22:11下载
- 积分:1
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FPGAVHDL
vhdl例程代码大全,包含流水灯,数码管,AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
- 2020-12-17 12:19:13下载
- 积分:1
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CHANNEL_ESTIMATION_PROJECT
基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)
- 2013-04-22 19:29:00下载
- 积分:1
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PIDcontrolbook2
PID CONTROLLER HELPING BOOK
- 2009-03-26 18:18:04下载
- 积分:1
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prac2
VHDL implementation using mouse and monitor
- 2009-06-28 20:10:56下载
- 积分:1
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FPGA realize for a good vga display routines, vhdl language.
针对FPGA一个实现vga显示的很好的例程,vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
- 2022-01-24 09:45:51下载
- 积分:1
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3.4
移位除乘法器带testbench好用的工程(Useful addition to the shift multiplier works with testbench)
- 2011-07-26 10:54:46下载
- 积分:1
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分:1