Using Verilog to write a serial transmission to the parallel transmission of the...

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code

为了便于计算结果在FPGA中后续的计算和ip核中的调用，本代码输入信号为普通浮点型数据，输出为32位表示的浮点型数据。

vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)

CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频(CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion)

i2c配置SAA7113，非常有用的程序，做视频采集类必看(i2c configure SAA7113)

altera usb 下载线DIY完全资料-altera usb blaster

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )