Using Verilog to write a serial transmission to the parallel transmission of the...

these are verilog files but i am uploading in text(notepad) format

基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode

VHDL语言的cookbook,能够使你更快的学会使用VHdL-cookbook

This code for countor . it is design in verilog HDL.

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

警卫控制系统，主要 控制 电梯系统 ，通过422通讯格式完成与电梯系统之间的 通讯协议。-Security control system, the main control elevator systems, through to complete the 422 communication format, communication protocol between the elevator system.

pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)