利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的

verilog编写的全功能串口-verilog programme of serial port

mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan

利用dsp builder设计的IIR滤波器，已经验证完全可以使用，只需要把其中系数改变。内含VHDL代码(Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)

编写 VHDL 代码为 4 x 1 多路复用器，使用下面的方法 (1) if else 语句 (2) case 语句 (3) 与声明

说明：  本资源有一个matlab程序段，是仿真BPSK分别在高斯噪声和瑞利衰落下的误码率，产生图形对仿真值和理论值进行比较(This resource has a matlab program segment, which is the bit error rate of simulated BPSK under Gaussian noise and Rayleigh fading respectively. The generated graph compares the simulated value with the theoretical value.)

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)

The deep lecture notes for basic digital system for cmos design