利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的

在这里设计的是时分复用系统，就是要将三路8比特数据复用到同一信道上进行传输(Here is the design of time division multiplexing system, is to take the road three 8 bit data multiplexed onto the same channel for transmission)

this a test keyboard code -this is a test keyboard code

Run-Length Encoder Example: Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07 Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07

HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)

Convolotional Decoding Based on Viterbi Algorithm

合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box

Kluwer academic the verilog hardware description language fith edition

滤波器 Generaic FIR Filter(Generaic FIR Filter)

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创-XC95144 stepper motor drive source, using verilog vhdl development, personal originality