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fftshixian
基于FPGA编写的verilog代码,在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)
- 2015-04-05 11:42:08下载
- 积分:1
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Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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bt656p
BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)
- 2020-12-09 12:09:19下载
- 积分:1
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Verilog-design-and-identify-book
找到这本书的完整版了。呵呵,贴出来和大家共享。这是本好书,我买了一本作为Verilog的参考书。这本书语法部分集中,便于查阅,此外讲了很多实用的设计思想。最重要的是本书薄,可以完整看完。强烈推荐。
(如果只是查阅,电子版就可以,如要完整学习,建议还是买纸质版的)(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))
- 2012-06-07 21:58:19下载
- 积分:1
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429recive
实现FPGA接收429板卡发送的信号,并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)
- 2015-11-26 11:18:19下载
- 积分:1
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BCD-counter
一个2位的BCD码十进制加法计数器电路,输入为时钟信号CLK,进位
输入信号CIN,每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT,输入时钟信号CLK用固定时钟,进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分:1
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Traffic-lights-at-the-crossroads
一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)
- 2013-05-16 10:18:38下载
- 积分:1
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用VHDL语言仿真交通灯
用VHDL语言仿真交通灯
用VHDL语言仿真交通灯
用VHDL语言仿真交通灯-Simulation using VHDL language VHDL language with traffic lights traffic lights Simulation
- 2022-01-26 03:57:23下载
- 积分:1
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described dds direct digital frequency synthesis of the basic tenets addition to...
讲述了dds直接数字频率合成的基本原理,同时用VHDL语言编写dds原代码用于生成正弦波,并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
- 2022-07-08 20:48:31下载
- 积分:1
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code
说明: 基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)
- 2021-04-14 13:38:55下载
- 积分:1