altera several new FPGA configuration methods and the use of experience

一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)

Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)

Control with DAC conversion

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

说明：  利用FPGA实现对外设按键的控制，例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)

本代码实现了 ； ；CORDIC  ； 算法语言；