altera several new FPGA configuration methods and the use of experience

EDK tutorial 1 ----------------

vhdl random numbergenerater

说明：  LVDS De-serialization

说明：  AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.

说明：  FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)

你的任务是为一个单一的"传统"的先进的电梯控制器的设计 电梯（即，简单的向上/向下按钮呼叫电梯） 在四楼经营 建设。所述的基本单电梯设计规范 以下各节。 扩展您的两部电梯的设计是可选的将会奖励你额外的奖金。

乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP

代码风格非常好，容易看懂，移植性高

电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件-Voltage pulse control of a project- including VHDL source code and compile the relevant documents after