Timer programming, vhdl language, can be achieved when the system timer 24

vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809

脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)

使用Verilog HDL来控制机器人，六个高精密舵机，舵机运动非常流畅，舵机不抖动(FPGA to control the robot servo, six servos)

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

program for half subtractor.

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog