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CORDIC_ATAN
使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)
- 2008-12-24 11:31:00下载
- 积分：1
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bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
- 2023-01-08 07:50:03下载
- 积分：1
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关于两种实现pwm的方法 基于51单片机设计
关于两种实现pwm的方法 基于51单片机设计-on two methods to achieve PWM 51 microcontroller-based design
- 2022-01-26 05:09:13下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
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用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有...
用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有 -Use VHDL to realize the digital frequency synthesis technology, almost the whole of, all have
- 2022-02-04 17:07:58下载
- 积分：1
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嵌入式应用开发技术白金手册源代码
嵌入式应用开发技术白金手源代码...
嵌入式应用开发技术白金手册源代码
嵌入式应用开发技术白金手源代码-this is a vhdf code
- 2022-04-28 14:40:01下载
- 积分：1
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fifo
高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)
- 2007-08-22 10:48:45下载
- 积分：1
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juchibo
用vhdl语言生成锯齿波，数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)
- 2011-12-21 19:29:51下载
- 积分：1
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dengjingdupinlv
等精度测频原理的频率计程序与仿真。。希望大家能用的到撒(such precision frequency measurement principles of Cymometer procedures and simulation. . Hope everyone can withdraw to the)
- 2006-06-09 18:15:07下载
- 积分：1
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esvl
MATLAB Filter Design HDL Coder
Simunlink HDL Coder
Xilinx ISE Webpack
- 2011-06-15 19:56:11下载
- 积分：1
