VHDL产生时钟50分频程序，供初学者参考

in this code very useful for designing real number concept

通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

书名：LDPC原理与应用。是国内第一本介绍用LDPC编、译码基本原理及应用技术的一本书。对用 vhdl 或verilog实现硬件编程LDPC的人开发无线通信是很好的资料(Title: LDPC Principles and Applications. Is the first book describes using LDPC Encoding and Decoding the basic principles and application of technology, a book. Right to use vhdl or verilog hardware programming LDPC people to achieve development of wireless communications is a very good information)

altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)

Digital pre-distortion (DPD) is an advanced digital signal-processing technique that mitigates the effects of power amplifier (PA) nonlinearity in wireless transmitters. DPD plays a key role in providing efficient radio digital front-end (DFE) solutions for 3G/4G basestations and beyond. Modern FPGAs are a promising target platform for the implementation of flexible wireless DFE solutions, including DPD.

lgpl RS编解码 5-6 Reed-Solomon Codes-LGPL RS codec 5-6 Reed-Solomon Codes

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

资源描述VGA视频图形阵列（VGA）接口是一三排15针de-15连接器。15针VGA接口是许多视频卡，发现电脑显示器，以及一些高清晰度电视机。在笔记本电脑或其他小型设备，迷你VGA端口有时用于全尺寸的VGA接口的地方。