VHDL产生时钟50分频程序，供初学者参考

基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器(Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors)

说明：  VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938(VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel)

modbus通讯必须的校验码生成器，可以直接使用(modbus crc16/8 free use)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!

FIFo参考设计16x32 FIFO with simultaneous read/write operations.-FIFO design-16x32 FIFO with simultaneous read/write operations.

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

Building the CPU datapath

经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)