VHDL产生时钟50分频程序，供初学者参考

quartusII的环境下的基于Ep3C10144的KeyBoard程序-quartesII of the environment based on the KeyBoard program Ep3C10144

说明：  Micron公司m73a系列nand flash仿真模型及测试文件(micron m73a series nand flash simulation model and testbench)

VHDL数字系统设计和工程实践3，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, 3, including the principles, truth table and schematic, as well as VHDL source code.

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

de2 70 开发板的演示程序，verilog语言编写，视频输入输出(de2 70 development board demo program, verilog language written, video input and output)

说明：  SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)

VHDL的四选一选择器-VHDL four elected a selector

this come from alter ,you can look and find it on line about USB