VHDL产生时钟50分频程序，供初学者参考

这是我自己写的两个8位二进制数的乘法程序，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote two eight binary number multiplication procedure, In xilinx Spartan3E debugging has been successful, with the show to share with you!

Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.

VHDL语言实现时钟程序，用fpga开发板试过后，能够执行-VHDL Pang Sung-wife of mother

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

开关电源变换器（Switching Power Supply）为当前电子产品中应用非常广泛的功率器件，在日常生活中无处不在

verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

verilog lcd2864 适合初学者(verilog lcd2864 )

本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching

a code to display in VGA using VHDL lang