VHDL产生时钟50分频程序，供初学者参考

AMBA设计和AHP桥梁SoC解决方案和测试策略。它是利用Xilinx和SIM模式和综合结果表明握手的两个通信协议 之间更好的预测。的设计示出了在有效的面积和速度方面。

关于FPGA排序算法的研究文献，有全排序和一些归并算法的文献介绍。(FPGA sequencing algorithm on the literature, there are some sort of sorting algorithm and the literature on the merger.)

长帧同步时钟的产生， 源码程序，实验好用(Long frame synchronization clock generation, source program, easy to use experimental)

自动售货机VHDL程序与仿真的vhdl的源代码-Vending machine VHDL procedures and simulation of vhdl source code

说明：  我测试过的！Verilog HDL实现RS编码。(I' ve tested it! RS coding Verilog HDL implementation.)

GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件-GAL16V8 disassemble source JED2ABEL.C the JEC document compiled abel

欢迎大家使用该程序，是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.

基于DE2开发板的VGA显示模块，仅供大家参考-DE2 development board based on the VGA display module, for your reference

是我们在在实验室做的摸60计数，并用LED显示出来。-is done in the laboratory in the loss of 60 counts, and LED show.

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram