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project_1
说明: 简单的一个Verilog小程序,适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分:1
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六个数码码动态扫描接口程序,用VERILOG语言编写的
六个数码码动态扫描接口程序,用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language
- 2022-03-24 21:40:23下载
- 积分:1
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使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享
使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
- 2023-08-12 00:15:02下载
- 积分:1
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一个视频信号输入的verilog源代码,里面含有相关的使用文档。...
一个视频信号输入的verilog源代码,里面含有相关的使用文档。-A video signal input of the Verilog source code, which contains documents related to the use.
- 2023-02-03 13:40:04下载
- 积分:1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立,能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分:1
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FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
- 2022-09-14 14:30:09下载
- 积分:1
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pinlvji
用汇编语言设计的频率计,注释较详细,适于初学者学习使用(Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use)
- 2012-04-16 10:47:59下载
- 积分:1
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verilog
数字信号除了的FPGA实现的Verilog源代码,之前发过一份是VHDL,各有所需吧,需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
)
- 2012-02-25 15:06:35下载
- 积分:1
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vhdl对dds的原理设计,由衷要得论文价值。不后悔
vhdl对dds的原理设计,由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets
- 2022-07-26 10:48:53下载
- 积分:1
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cordic implementation in vhdl&c
cordic implementation in vhdl&c
- 2022-10-31 01:55:03下载
- 积分:1