Verilog语言手册

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

It is vhdl code for defining a finite state machine

SHA256加密过程,非常详细，内附原码，还有文档，很可用~(SHA256 encryption process, very detailed, containing the original code, as well as documents, it is available ~)

pll(phase locked loop) is used to fix the circuit to particular frequency

wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)

LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details

十进制精确计数，经典写法，便于学习与参考，供大家分享-Decimal precision counts, classic written, easy learning and reference for all to share

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)

用Verilog实现的脉冲宽度调制程序，在quartus平台上测试成功。(Using Verilog implementation of pulse width modulation, in quartus platform test successfully.)