Verilog语言手册

十六进制计数器递增 ALTERA FPGA 板 7 段显示器上的每一秒。

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

100个VHDL的例子-100 examples of VHDL

mike11河道断面处理软件，将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format )

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.

说明：  bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过 (mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)

串口控制器，基于vivado软件下开发，包含代码及管脚分配文件(Serial port controller)

axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)