Verilog语言手册

说明：  ip core of the transceiver gtx

一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)

Block LU decompostion of a matrix

65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process

这是一个基于FPGA实现的GPS的程序，保证可以用-This is an FPGA-based GPS program to ensure that you can use ... ...

This is a divider, which is depicted as well. It is a programming language Vhdl.

A ROM to build a squaring circuit

完成RS（5，3）编码程序，运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)

32bit floating point addition

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)