proficient VerilogHDL : IC design example explanation of the core technology

JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits

16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)

code for fft non synthesisable in xilinx ise

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

一个液晶灯的小程序。我没有写信。我只负责调试。适用于ACEXEP1K30QC208-3。我运行模拟器，标记连接销。我接下来在电路板上试了试，没有问题。实验中使用的板兄弟把CLK1的TESTOUT3改成了合唱或0。新人在线帮助是每个人的责任。

pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test

此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用 (This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)

说明：  sd_sdram_lcd 是读取SD卡中的数据，然后通过LCD显示(It is to read the data in SD card and display it by LCD)

VHDL Vendingmachine source