m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...

用verilog语言编写的串口读写程序，波特率可调，亲测可用。(this is a program for UART by verilog, which is useful.)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err

这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences

采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric circuit, the gate control the electric circuit and the decoding circuit

完成交通灯的所有功能，已经通过验证。希望大家多多指教。(Completion of all the features of traffic lights, have been authenticated. Hope the exhibitions.)

六十进制计数器用于计数等操作，代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)

实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态(dianti in verilog)

vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful

三十个vhdl源码，对于刚开始学习vhdl的很有帮助，可以帮助理解数字电路-30 vhdl source for the beginning of the study vhdl helpful, and can help to understand digital circuit