能够实现8位的无符号数的乘除法，模拟了笔算的过程

在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files

FFT VHDL code

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)

fpga debounce filter code in vhdl

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

用FPGA实现 VGA显示的图像显示控制器设计 用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design Using VHDL hardware implementation is colored stripes appear above the screen)

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

说明：  基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)