收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。...

说明：  基于EasyFPGA030的直流电机控制电路设计和四位数字密码锁。(DC Motor Control Based on EasyFPGA030 circuit design and four-digit combination lock.)

cvery high compatibles for quartus

本文档介绍了通用异步收发器（UART）VHDL 组件，它可以使用，也可以与PmodRS232或与一个板上的RS232端口。一个UART 部件被用于转换串行数据为并行数据，并且并行数据为串行数据。串行 转移到UART数据被放置在一个输出总线经过了UART将其转换成并行 信息。该总线可以被用作输入到其它逻辑门阵列中。所得到的数据可 然后再次使用UART组件被送回了串行。

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,

iic 总线 verilog 源代码 标准i2c总线， 有sda scl 时钟，频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

FPGA实现DDS波形发生器，多种信号的产生，(FPGA realization of DDS waveform generator to produce a variety of signals,)

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)

fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，(fftpoint 1024 verilog code)