多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_...

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

说明：  Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)

FPGA源代码公布，包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序，LED静态显示ADC0809 VHDL控制程序，DAC0832 接口电路程序

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

Real time Clock DS1307 interacing with PIC using I2C.

适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)

有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)