VHDL example code

基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated

数字逻辑课程设计，用vhdl实现红外线传输系统的课程设计，下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

在 FPGA，SPI、 I2C 等 ASI，串行接口的实现来武力作为需要实现外围设备之间的接口。这个项目给 VHDL 源代码实施 SPI 接口和他们有关的文件。

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)

应用背景用键盘上的应用程序，如文字，以矩阵为主导。关键技术键盘的PS / 2在DE2 115编程。它是有用的，重要的是要了解如何在DE2用VHDL键盘程序

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL

基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!

在nios系统开发中的驱动i2c音频电路的代码,包括verilog代码,与相应的驱动代码(In the nios system development in the driver i2c code for the audio circuitry, including the verilog code, and the corresponding driver code)