完整的 USB

morris mano basic vhdl code in ise

频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)

stratixIVGX，芯片4sgx230es，SDI测试完整工程，实现SDI的收发(stratixIVGX，SDI Receive and Transmit)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable

使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,(the modulation of 16QAM based on FPGA)

自己完成的项目，成功用vhdl语言实现数字跑表，可存储。

用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim

UVM 1.2 golden code, (code for UVM, )

典型事例，从网上down的，希望对大家有用，-Typical examples, from the Internet down, and I hope useful for everyone,