用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260

3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products.-3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other products.

乘数是其中一个关键硬件块在大多数数字和高性能系统中如 FIR 滤波器、 数字信号处理器和微处理器等。随着技术的进步，许多研究者试过和正在尝试设计提供或者以下高速度、 低功耗、 规律的布局的乘数，从而较少的地区或在乘数的他们甚至组合。从而使它们适合于各种高速度、 低功耗，和紧凑的超大规模集成电路的实现。然而面积和速度是两个相互冲突的约束。所以提高速度结果总是在较大的地区。所以在这里我们尝试找出解决方案了他们两个之间的最佳贸易。一般我们所知乘法会中两个基本步骤。部分产品，然后添加。因此在这个项目中我们有第一次尝试设计不同加法器和比较它们的速度和复杂性的电路即占领的地区。

Vhdl Golden Reference Guide.pdf

等精度测频原理的频率计程序与仿真。。希望大家能用的到撒(such precision frequency measurement principles of Cymometer procedures and simulation. . Hope everyone can withdraw to the)

This file contains async fifo design

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

基于FPGA的16QAM调制器设计与实现(Design and implementation of 16QAM modulator based on FPGA)

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)