ht82v38 线性ccd AD转换fpga程序

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

moving tracking based in D5M camera tracking camera

基于VHDL实现（7，4）汉明码的编码器和译码器(VHDL-based implementation (7,4) Hamming code encoder and decoder)

65位FIR数字滤波器的设计~~其中有通过仿真得出得数据 ~可以通过数据输入完成滤波实验~对数字滤波器得整个算法进行了分析包括输入分组相加 然后相乘得过程-65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multiply in the process

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal

FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)

用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)

对于32位寄存器前导零个数的计数，一个简单的程序(32 registers a leading zero number of counts, a simple procedure)

本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.