verilog prescaler for the realization of the odd

Disparity mapp code in VHDL

VHDL_COUNTING 000_255 液晶显示器 (ĐẾM 000 ĐẾN 255 HIỂN THỊ 液晶电视 BẰNG NGÔN NGỮ VHDL)

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand

The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.

说明：  关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

SPI协议的VHDL/Verilog语言实现。(SPI agreement VHDL/Verilog language.)

以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

说明：  潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)