附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，...

中科院VHDL学习资料，很好的东西，希望对大家有用-Chinese Academy of Sciences VHDL learning materials, a very good thing, everyone would like to be useful

说明：  文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)

一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

用Verilog 写一个8x16 的FIFO，完成先入先出的功能，并且在FIFO读空时输出EMPTY 有效信号，读指针RP 不再移动；FIFO 写满时输出FULL 有效信号，并且即使WR 有效也 不再向存储单元中写入数据(写指针WP 不再移动)。 (NO)

电子表，实现计时记分计秒的功能，同时可以对时分秒进行校正，实现调时功能。-Electronic watches, time points of dollars to achieve a second function, at the same time when the minutes and seconds can be calibrated to achieve when the transfer function.

eda的入门学习课件，老师不错，内容页挺好的(eda learning files)

基于DDS的BPSK调制器设计Verilog源码( U57FA u4E8.08 u868)

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)