附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库，创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化，...

first in first out 的说明文档以及时序图 对学习FIFO很有帮助(first in first out the documentation and the timing diagram helpful in learning FIFO)

详细介绍modelsim的使用方法，详细的介绍modelsim使用方法-Details on the use of ModelSim, ModelSim detail using the method

光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)

一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter，explained about the realization of multi-channel and simulation )

vhdl code for carry lookahead addder

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

VHDL数字电路设计教程 乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)

用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.