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fifo_ref_timing
first in first out 的说明文档以及时序图
对学习FIFO很有帮助(first in first out the documentation and the timing diagram helpful in learning FIFO)
- 2010-07-21 21:43:36下载
- 积分:1
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详细介绍modelsim的使用方法,详细的介绍modelsim使用方法
详细介绍modelsim的使用方法,详细的介绍modelsim使用方法-Details on the use of ModelSim, ModelSim detail using the method
- 2023-01-21 22:25:05下载
- 积分:1
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GTX4
光纤发送接收模块,verilog编写,主要用于光纤的发送和接收,波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)
- 2016-06-28 14:06:40下载
- 积分:1
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paper_about_polypahse
一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter,explained about the realization of multi-channel and simulation
)
- 2014-11-21 22:32:22下载
- 积分:1
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claa
vhdl code for carry lookahead addder
- 2014-02-05 00:26:26下载
- 积分:1
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FPGA_CPLD-SHC
FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图,很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)
- 2013-03-04 23:36:01下载
- 积分:1
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VHDLshuzidianlushejijiaocheng
VHDL数字电路设计教程
乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)
- 2010-08-07 10:37:05下载
- 积分:1
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pidd
VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)
- 2020-11-13 10:09:43下载
- 积分:1
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textiowrite
quartus ii 环境下,一个完整的利用TEXTIO仿真的源代码,包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分:1
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用例化语句和case语句编写的全加器的VHDL描述。
用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.
- 2022-01-26 02:45:15下载
- 积分:1