all passed, I was carefully designed, fully meet the requirements of beginners....

design cpu 16 bits by verilog HDL.

Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)

Quartus II软件设计数字电子钟，使用verilog语言编写各个 模块生成symbol files，再用原理图方式制作顶层文件。 完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能； 具有整点报时功能，声响电路发出叫声； (failed to translate)

大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.

用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the

moving tracking based in D5M camera tracking camera

Vhdl code for aarithmetic logic unit

说明：  Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)

Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)

2位并行加法器初学者必看初步了解FPGA-two count