cpld/fpga common adder Verilog design procedures

介绍如何使用 FPGA 内部的 ROM 以及程序对该 ROM 的数据读操作。(This paper introduces how to use the ROM inside the FPGA and how to read the data of the ROM by the program.)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

VHDL Programmes -2 for dumping on FPGA

Altera QUARTUS 7.2的矩阵键盘电子琴完整工程（含源码），在EP2C20芯片上实现-Altera QUARTUS 7.2 Project of matrix keyboard electronic organ, implement on EP2C20 chip.

用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure

amba ahblite总线时序转并口时序，可访问sram/flash/mram，适用于smartfusion2系统，arm内核对外进行数据访问。

说明：  FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)

用VHDL语言实现8-3线编码器，16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)

 本程序应用VHDL硬件描述语言，以QuartusⅡ8.0为开发工具设计了一个具有自动演奏乐曲功能的系统，演奏乐曲为《梁祝》，具有单曲播放器功能。本程序简单易懂，可作为FPGA入门学习之用。