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此示例是8051核加频率计的联合设计,带有8051IP核资料
此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
- 2022-06-14 22:57:42下载
- 积分:1
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OFDM_CP
ofdm系统的matlab实现,包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分:1
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this is the for a equiripple filter
this the for a equiripple filter-this is the for a equiripple filter
- 2022-04-17 20:07:48下载
- 积分:1
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PWM的产生
这是脉冲宽度调制技术的VHDL代码,包括一个比较器,正弦波发生器,锯齿波发生器,脉冲宽度调制器等。
- 2022-08-08 11:19:53下载
- 积分:1
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gps_lms
本系统用于GPS中频部分的窄带滤波(AD后的数据经过LMS滤波后去掉窄带干扰,可以抑制20dB以上的干扰)(this system can be imply to anti-narrowband-jamming for GPS IF signal, it can degrade 20dB narrowband jamming)
- 2011-08-23 21:06:41下载
- 积分:1
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altera公司cpld/fpga开发软件quartus2中文使用教程
altera公司cpld/fpga开发软件quartus2中文使用教程-altera company cpld/fpga development of software to use Chinese quartus2 Guide
- 2022-11-23 18:50:03下载
- 积分:1
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receiver
一个LED大屏幕接收卡的完整设计工程,有需要学习LED大屏幕控制的朋友可以参考
- 2010-02-28 12:18:21下载
- 积分:1
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rtl
SPI verilog RTL code
- 2016-02-29 12:26:08下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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frequency divider
说明: FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1